On the wafer floor, a 2°C drift during soft bake isn’t just an offset—it’s scrap. Photoresist sensitivity, line-width budgets, and defect targets all hinge on heat that’s repeatable and uniform. When the thermal profile wobbles, you get scumming, adhesion issues, and particle excursions that don’t show up until later in the line. What matters under the hood We build custom infrared heaters around the thermal realities of wafer processing, picking short-wave or medium-wave sources to match your absorbance and cycle time. The whole point is wafer-level uniformity, held within ±0.1°C across the heated zone, so the photoresist bake stays inside the process window. Temperature repeatability comes from a calibrated sensor loop and stable emitter response, not from chasing setpoint with big overshoot. The units are rated for cleanroom Class 1–100, with quartz or ceramic assemblies and sealed termination paths that keep particle generation at zero. Power density is tuned to your tool footprint and voltage class, and the connector options line up with existing fixtures, so integration is straightforward mechanical and electrical, not a hack job. Why this plays in lithography and bake tracks This precision shows up as fewer rework lots and tighter critical dimension control. Soft bake and hard bake profiles stay stable across lots, with less edge bead variability and fewer residues. Energy use drops because the heater hits setpoint fast, then idles clean without wide cycling. Reliability is built for 24/7 operation, with emitter life that supports long campaigns and minimal maintenance interruptions. The payoff is consistent yield and predictable uptime—fewer excursions and less bake-related scrap. The things you need to get right up front These heaters are tool-specific by design, so mounting, aperture size, and view factor have to be confirmed against your chamber geometry. Clearance to optics and sensors matters—thermal radiation can couple into nearby components if the layout isn’t reviewed. Expect a short commissioning run to finalize PID tuning and confirm uniformity maps across product wafers. Once matched, the profile stays stable, but that initial fit is part of the installation, not an afterthought.